Miniaturized Electronics Development Center --> Publications --> #1
MINIATURIZED ELECTRONICS FOR SPACE FLIGHT APPLICATIONS
H. D. Voss*, J. R. Kilner, R. A. Baraze, J. Mobilia, D. L. Chenette, R. W. H. van Bezooijen, E. Aamodt,
Lockheed Palo Alto Research Laboratory, 3251 Hanover St., Palo Alto, CA 94303
R. B. Kash, A. J. Goodwater, and E. Kwok
KMOS, 1012 Stewart Dr., Sunnyvale, CA, 94068
Reductions of 10 to 100 have been realized in the size, weight, and power of space flight electronics while improving reliability and reducing fabrication costs by using custom and semi-custom VLSI microelectronics and sealed (5000 Angstroms of Si3N4) chip-on-board (COB) assembly. Both the mixed mode microcircuits and COB process have recently been approved by NASA for the ISTP/GGS satellite program. Mixed-mode analog/digital integrated circuits have flown on the TIROS-I spacecraft (MAXIE instrument), and will be flown on the NASA/ISTP POLAR spacecraft (SEPS, PIXIE, and CEPPAD/IPS instruments) and the P91-1 ARGOS spacecraft (SPADUS instrument). The analog portion of a single array microcircuit contains about 80 operational amplifiers which may be used as low noise amplifiers, filters, A/D and D/A converters, sample/hold circuits, or voltage references. About 55% of the array is available for digital circuit functions. The base array for these devices is designed for radiation hardness and the CMOS process allows for low power, typically 20 mW per chip. Three microcircuits using this array were developed for the SEPS instrument are described: 1) a 16-channel low noise front-end amplifier chip with D/A converters and coincidence logic; 2) a flash pulse height analyzer chip with eight 16-bit scalers with overflow; and 3) a general purpose input/output chip with A/D and D/A converters, parallel and serial ports, clock oscillator, counter-timer, interrupt controller, decoder, and other functions. A prototype CCD analog microchip that includes camera related control and spacecraft interface IO functions was developed.I. Introduction
The driving requirements for space flight micro-circuit technology are low power, low weight, radiation hardness, and high reliability at a reasonable cost for very limited production orders. Miniaturized electronics has been accomplished using semi-custom gate arrays1 (Table 1), and sealed-chip-on-board packaging. Recently, flight quality CMOS Programmable Logic Devices (PLD's) for digital electronics have become available at reasonable power levels and cost. However, for analog circuits and very low power digital circuits, discrete elements are still in widespread use. It has been our experience that a 10 to 100 fold reduction in space flight electronics can be realized using combined analog and digital (mixed-mode) gate array microcircuits.
A gate array microcircuit consists of a matrix of transistors and passive elements which are interconnected with only one or two custom metalization layers to make an application specific integrated circuit (ASIC). Because the matrix is mass produced and well characterized (semi-custom), the risk, cost, and turnaround time are significantly reduced as compared to a full custom microcircuit. The arrays are highly reliable since they significantly reduce the number of interconnections and discrete parts while permitting a parallel system architecture. The electronic weight, power, and size are significantly reduced with a semi-custom array. After initial design, circuit modifications require about a three week turnaround.Table 1: LPARL ASIC Design Experience
II. Base Array Architecture and Principles
The technology chosen for the mixed-mode microcircuit is a 4 micron CMOS process developed by KMOS2. This process yields a breakdown voltage range of up to 14V for the standard process and 11V for the rad-hard process. The KRAD array is designed to be radiation hardened up to a Megarad and uses an epitaxial substrate to prevent latch-up. The die size for the KRAD is 0.45 inch (11.4 mm) on a side to accommodate the necessary circuit components and the 86 signal pads. Smaller versions are available from KMOS in non rad-hard form (e.g. KM1 to KM16 series). The standard process also includes an epi-base to prevent latch-up.
A photo of the KRAD die is shown in Figure 1. About 45% of this die is used for analog functions and interconnections and 55% for digital functions and interconnections. The circuit components available to the designer for the KRAD array are given in Table 3.
To obtain radiation hardness, the KRAD was designed with N-channel stops (guard-bands) for all of the devices. The base wafer was produced at two foundries. The results are summarized in Table 2. The data were obtained with a certified Co-60 source and represent levels in rads-Si where the channel thresholds began to drift. KRAD devices made at ECI were hard to well over 5 Megarads; the Orbit foundry process has not yet been tested using their high-rad process. On the medium-rad process at Orbit the KRAD was rad-hard to 4 x 104 and 3 x 105 rads-Si for the analog and digital sections, respectively. The amount of threshold shift depends on the analog components and the foundry process.
The capacitors have a polysilicon-oxide-heavy P+ implant structure and are designed with a unit capacitance of 1.0 pF. They are available in groups of 2,4, and 8 capacitor blocks.Table 2: Rad-Hardness for Analog/Digital Gate Arrays
Table 3: KRAD-Hard CMOS Base Array Components
Quantity Feature Channel W/l 86 Pads, ESD protected (microns) Low Power CMOS Technology (e.g. 20mW/chip) Analog Section 22 Low impedance output buffers 1000/4 N 42 Low noise/low imepdance FETS 2000/4 P 225 L-cells, drivers 150/4 N, 150/4 P 225 M-cells, 4P & 4N 45/11 N, 90/11 P 75 Hi-Z transistor resistors, up to one megohm 1575 Capacitors, 1 pf each 225 P-well resistors, 160 K-ohm/string, 20 K-ohm taps, ~2%/volt ~30000 Poly-Si resistors, 120 ohm/segment, no change with voltage 360 Cap implant resistors, 12 K-ohm each, ~0.2%/volt Typical Current for an OP AMP is 10 to 15 µamps, 8 Mhz GB product Digital Section 64 Low impedance output buffers 1000/4 N 1200 Core-cells, 4P & 4N 80 Core-cells, 4P & 4N, small switch cap 640 Cap-implant resistors, 12 K-ohm ea. , ~0.2%/vol ~50000 Poly-Si resistors, 120 ohm/segment Typical propagation delay ~3 ns, Risetime ~4 ns, Max clock ~20 Mhz.
There are three kinds of fixed resistors available; diffused P-well, cap implant, and polysilicon. The P-well resistors are available in strings of 160 K-ohm with 20 K-ohm taps. The cap implant resistors are available at 12 K-ohm each. The polysilicon resistors that are available are the "underpass" or "crossover" interconnects. These resistors have no measurable voltage coefficient and average about 120 ohms each.
The analog and digital cells contain transistors of different sizes as indicated in Table 3. There is room on the KRAD for over 60 equivalent operational amplifiers and these can be designed application specific with the internal passive components. The 2000/4 W/L ratio P devices and 1000/4 W/L ratio N devices are adjacent to the analog section bond pads and can be used as low-noise input stages or as low- impedance output buffers
III. Analog / Digital Microcircuit Modules
To design and develop analog/digital gate arrays, use is made of simulation tools, PLD's, amplifier kit parts, and libraries of macro modules. For "breadboarding" the digital portion of a gate array, computer simulation tools can be used to program a PLD and/or a gate array design without any wiring. SPICE can be used for analog simulation with good results, however, it is usually advantageous to build a partial breadboard using kit parts when pioneering new designs. For the bulk of many designs, standard analog modules that have been proven and characterized on the gate array can be easily modified to meet the new requirements. Table 4 shows a partial list of these modules.
Much of the proposed new space flight instrumentation is based on the demands of sophisticated sensor electronics. To simplify instrument development, improve performance, and reduce spacecraft resources, the design and development of three modular and programmable KRAD microchips was undertaken in conjunction with new sensor interfaces (i.e. solid-state detectors and microchannel plate sensors). Figure 2 illustrates the key microcircuit modules which have been developed as part of the NASA ISTP/GGS SEPS program.
The Source/loss-cone Energetic Particle Spectrometer (SEPS) is an advanced imaging particle spectrometer designed to continuously monitor particle energy (E>20 keV), angle of arrival, and ion/electron ratio with high time resolution. This instrument design illustrates some of the new capabilities for mixed-mode microcircuits and sensor interfaces.
A 6.5 cm2 by 200 micron thick solid state sensor was developed by Hamamatsu Inc. for SEPS with individual readouts of 256 pixels (see Figure 2). The individual pixels minimize detector capacitance (i.e. low energy threshold) and crosstalk compared to strips and allow for fast parallel processing. The proton dead zone for this device was found to be 8 keV and energy resolution at room temperature was 2 keV FWHM. Six of these sensors (using 768 amplifier strings) are included in the SEPS instrument which has a power budget of 3.5 W.Table 4: Partial Cell Library for Mixed-Mode Designs
Cell Type Preferred Characteristics •Data Conversion A/D converters •10-bit Successive Approximation, 10 µsec Conversion time +/- 0.5 LSB •8-bit Flash, 300 ns, +/- 0.5 LSB D/A converters •Resistor string up to 12 bits, Integral non-linearity +/- 1/2 LSB Conversion Rate to up 1 MHz Sample & Hold •10 bits in 1 µs, Droop of 1mV/ms •Operational Amplifiers General Purpose • Gain 80 dB, Bandwidth 3 MHz, Phase margin 70ˇ, Slew 4V/µs, ±5V • Gain 100 dB, Bandwidth 8 MHz, Phase margin 70ˇ, Slew 20V/µs Comparator • Gain 80 dB, 500 ns response for 20mV overdrive, input offset ~5mV Others • Programmable Logarithmic Gain, autozero, chopper stabilized, phase locked loops, instrumentation amps. •Analog-Switch • 2:1, 8:1, 16:1, ... Analog Mux. On resistance 200, up to 10mA •Time Reference • Up to 15 MHz Crystal Oscillator • Voltage-Controlled Oscillator Timers and one-shots •Filters • Switched capacitor (1Hz-50 kHz) Continuos time up to 1 MHz Chebyshev, crystal clocks, chopper •Signal Conditioner • Peak, Averaging, RMS, Integral Demodulator, wide dynamic range •Power Voltage Reference • 10V, 5V, Bandgap Ref. 50 ppm/ˇC Converter • Voltage to Current Converter 70% eff., Output 0-20 mA Regulators • 1.2V to 1.4 V, 0.1 % regulation Level Shifters • Input +/- 5V Output +/- 15V
To run hundreds of sensor elements using low power requires microcircuit technology to amplify and process the data. To achieve this goal, SEPS uses 54 front-end (FE) chips, 12 pulse height analyzer (PHA) chips, and 6 data acquisition input/output (I/O) chips. These chips are all made on the KRAD base array. Using these chips, it was possible to design the instrument with a parallel architecture to eliminate single point failures
IV. Low Noise & Power Front-end (FE) Microcircuit
The first circuit on the KRAD to be described is an array of sixteen low noise front-end amplifiers with associated coincidence logic. The main features of this array are outlined in Table 5 and the analog design for one channel is shown in Figure 4. Input charge pulses as low as 20 keV (5700 electrons) are amplified and shaped for subsequent peak holding and pulse height analysis.
The input FET is a P-channel device with a W/L ratio of 4000 to 4 (two paralled P-channel devices). The input signals are DC coupled and a feedback transistor (Hi-Z device) is used to balance the input leakage current. The feedback capacitance on the folded cascode charge amplifier is 1.0 pF. Similar charge amplifier techniques have been used by Beuville5. Each FET input has a test input that can be pulsed through a 1 pF capacitor for calibration. After the charge amplifier, the step input signal is differentiated and further amplified with a 0.5 µs time constant. The output signal from the amplifier chain before the peak detector is shown in Figure 5. Comparators set by on-chip D/A converters trigger the coincident logic for particle identification by the PHA.Table 5: SEPS Front-end Gate Array Features
• 16 pre-amps -- each has a calibration pulser input, low gain (proton mode) and high gain (electron mode) sections, and test outputs via a diagnostic MUX for each gain. • 17 peak holding circuits -- 16 XY pixels and one E detector pixel. • 16 electron mode comparators with individually adjustable thresholds. • 16 proton mode comparators with a common adjustable reference. • Microcomputer data input to configure the chip. • Logic disable gates for each pixel and each anti. • Set-up latches (113 bits) to configure the chip. • Mode control latches. • Coincidence logic with adjustable resolving time. • Programmable anti coincidence logic including pile-up rejection. • Tri-state outputs controlled by a polling clock.
The single channel version (ECI process) of this chip was tested and survived radiation testing without analog or digital shifts up to 5 x 106 rads Si. The 16 channel version, on the medium radiation hard process of Orbit, was flight operational to 5 x 104 rads Si.
V. Pulse Height Analyzer (PHA) Microcircuit
The second circuit described is a 16-channel pulse height analyzer which accumulates multiple spectra in a dedicated RAM. Table 6 summarizes its features. Typically, this chip would process data from four front-end chips by polling a different one every 8 microseconds. The analog energy signal held by the front-end chip is analyzed and stored in 16-bit words in a dedicated external memory chip (8Kx8). Four pixel identification bits, two mode bits, and two front-end ID bits are used to route each count to memory. The mode bits are set by the front-end coincidence logic to specify particle type and energy range. As the system processor reads the accumulated spectra, a zero is automatically written into each word. Eight-bit DACs control the upper and lower limits of the stacked discriminator. A block diagram of the PHA chip is shown in Figure 6.Table 6: PHA/Scaler Gate Array Features
• 16-channel stacked discriminator (log/linear) with programmable endpoints set by two 8-bit DACs • Eight 16-bit scalers with overflow bits and buffers • 16-bit computer bus interface • Set-up latches (24 bits) • State logic directs the collection and storage of spectra in a dedicated 8Kx8 RAM • The RAM is organized as 4K 16-bit words • Data router and increment logic accumulate up to 256 16-channel spectra • Control logic to multiplex four front-end chips and isolate them from the computer bus • 3-to-8 decoder with five external outputs
The eight scalers use a common jam signal to transfer their contents to the output buffers and automatically clear the scalers. This chip may be configured to operate without front-end or memory chips. When an analog input (energy) pulse exceeds the threshold determined by the low DAC reference, a programmable length window opens during which the peak is determined. At the end of the window, one of the eight scalers is incremented. Two chips may be connected to make a 16-channel flash PHA.
VI. General Purpose Data Acquisition Chip
The third chip provides a versatile input/output interface between the onboard microprocessor (an 80C86 in the case of SEPS) and the instrument or the spacecraft. It can serve as the basis of a Data Processing Unit (DPU). A typical experiment would incorporate several of these chips. An effort was made to design the circuits of the data acquisition input/output (I/O) microchip to be general purpose and programmable.
The basic architecture of the chip consists of 12 modules. These are summarized in Table 7. The 12 modules are semi-independent and are linked together via a 16-bit bi-directional data bus which is driven by the processor. Figure 7 shows the I/O chip block diagram.
The programmable control registers configure the chip; many variations are possible. For example, the serial I/O may be input or output and either polarity of the clock and enable signals can be selected. A built-in crystal oscillator (15 MHz) generates the micro-processor clock, provides external clocks out and internal reference clocks for the counter/timer. The interrupt logic on several chips may be chained together. Individual interrupts are enabled by setting a bit in the mask register. The eight-input MUX on the 8-bit A/D converter may process the inputs as eight single-ended or as four differential signals. The D/A converter can be used to control external voltages or for changing the amplitude of pulses in the internal pulse generator. Power consumption for the I/O chip is less than 20 mW.Table 7: I/O Gate Array Features
• 16-bit computer interface with 4-bit address decode • Control registers (44 bits) • Serial input/output with an 8-bit buffer • Eight-bit counter/timer with an adjustable pre-divide • Watch-dog timer for resetting microprocessor • Digital-to-analog converter with a pulser mode • Analog-to-digital converter with an eight-input MUX • Dual eight-bit bi-directional parallel ports • Vectored interrupt logic (five internal). The three external interrupts may be edge or level triggered • Status register • Crystal oscillator (generates computer clock) • Power-on reset circuit
VII. CCD Camera System ASIC
CCD video imaging devices are becoming more popular for many space flight applications; including IR, optical, UV, X-ray, and energetic particle sensors. Reducing the CCD analog and control electronics using a general purpose CMOS rad-hard ASIC results in lower power, fewer parts, and diminishing per unit cost. Unique sampling circuits and log spaced flash A-to-D converters can be used for capturing and compressing rapid intensity information. Parallel processing of the CCD focal plane sectors is possible with an ASIC to improve readout speed and reliability.
The general purpose I/O chip was partially modified to include circuits for a CCD camera. Added to the I/O were a correlated double sampler circuit, analog multiplexer, and flash comparator stack. The General Purpose Interface (GPI) circuit for a CCD camera, based on the I/O chip, is shown in Figure 8. The analog circuitry (Figure 8) amplifies the CCD output signals, thresholds the signals, digitizes and formats the outputs to the computer. Each ASIC has two correlated double samplers to improve the signal-to-background ratio on a pixel-to-pixel basis. The boxes in Figure 8 with dagger symbols are existing parts of the I/O chip and are for general use to support the CCD camera CPU, health and safety functions, and command and TM interface with a spacecraft. The CCD GPI chip is currently prtotyped for the specific application of an autonomous star tracker instrument6.
VIII. Sealed Chip-On-Board
SCOB provides low cost, high density, low noise, fast speed electrical packaging, lower weight and better thermal management. Difficulties include selecting good known die, rework of SCOB parts, testing, and physical protection. Epoxy encapsulants applied over finished COB assemblies have resulted in limited success in providing an environmental barrier and a low stress matching of the thermal expansion coefficients. A high reliability and environmentally sealed barrier that is conducive to inspection, testing, and rework was developed by Ionic System of Salinas, CA.7. A thin barrier film of silicon nitride (.05 µm of Si3N4) is deposited at room temperature over the completed die bonded assembly. Testing and evaluation for the NASA GGS program consisted of finite element analysis and a variety of environmental and quality assurance tests. Mixed mode ASICs and SCOB technology can benefit electronics system for spacecraft and military applications and commercial products such as automotive electronics, high performance and compact ground systems, and lightweight portable electronics sensors. Figure 9 shows the SEPS instrument COB.
IX. Future Work
As mixed-mode microcircuit geometry shrinks, it becomes possible to increase functionality and speed while lowering power and cost. The other major task is to improve the simulation and layout tools so engineers can efficiently develop chips at low risk and cost. Our goal is to use in-house workstations to proceed from an idea to a completed layout disk for a microchip foundry. With this approach semi-custom microcircuits can be produced more efficiently.
Current space flight technology for CMOS analog and digital microcircuits operates between 5 and 15 volts. The need to reduce electronic power consumption in both ground based and space flight systems while maintaining performance is critical to many future technologies. By significantly reducing power consumption, the associated mass, volume, thermal loads, and eventual cost are indirectly reduced while the reliability is improved.
Substantial power reductions of one to two orders of magnitude, as compared to the existing ~20 mW/chip, are possible if a microcircuit can be operated near one volt. The prospects for micro-power IC's are summarized in Table 8. Many new possibilities emerge, such as: micro-power (about 100 mW) instruments for space flight, large neural network and computer systems, wide band imaging spectrometers, and micro-satellites (about 2W/satellite). Spacecraft power, thermal dissipation, solar array size, and cabling would be greatly reduced.Table 8: Micro-power IC Applications
• Micro-instruments for spaceflight (100 mW/instrument) - Simple PS, low EMI/weight, minimal S/C resources • Neural networks (1015 Connections/s, 1 FJ/connection) - 1 W Biology vs. 1 MW VLSI for 1016 Connections/s • Numerous groundbased applications - Battery powered devices • Wideband Imaging Spectrometers (>106 pixels) - New types of instrumentation • Micro-satellites (2W/satellite)
Some of the technologies integrated with the microcircuits include packaging (such as chip-on-board, flip chips, surface mount and hybrids), connectors, and sensor interfaces. Also, as chips become more sophisticated, testability must be designed into the circuit for rapid troubleshooting and diagnostics
The authors wish to acknowledge Mr. M. Hilsenrath at LMSC for assisting with the testing of the single channel FE chip and Mr. E. L. McFeaters for assisting with the quality manufacturing. Mr. W. Stansbury of Promex for COB assembly and bonding of the die. Dr. R. Kubacki of Ionic Systems performed the plasma Si3N4 sealing. M. A. Garrison of GSFC performed the NASA review of the SCOB process. We also thank Drs. T. R. Fisher, R. W. Nightingale, E. G. Shelley, and R. R. Vondrak of LMSC for their encouragement and support. Several students at Taylor University helped with the development of this paper. Thanks are extended to the NASA GGS team for supporting the SEPS advanced design and microchip development effort under contract NAS5-30622. This paper has been supported by the Lockheed Independent Research and Development Program under the direction of Dr. R. A. Kuiper and by the Taylor University Science Research Training Program.
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