FEA

• Front-End Gate Array Features

• 16 pre-amps -- each has a calibration pulser input,
         low gain (proton mode) and high gain (electron mode)
         sections, and test outputs via a diagnostic MUX for each gain.
• 17 peak holding circuits -- 16 XY pixels and one E detector 
         pixel.
• 16 electron mode comparators with individually adjustable 
         thresholds.
• 16 proton mode comparators with a common adjustable
         reference.
• Microcomputer data input to configure the chip.
• Logic disable gates for each pixel and each anti.
• Set-up latches (113 bits) to configure the chip.
• Mode control latches.
• Coincidence logic with adjustable resolving time.
• Programmable anti coincidence logic including pile-up rejection.
• Tri-state outputs controlled by a polling clock.

• Current Designs

  • Internal Preamp
    Used in Polar/SEPS chips
    

  • External Preamp
    (A225 or A250 input)
    Used on IMAGE/HENA SSD chip
    

  • External JFET input