| From DPU: | |
| SEL* | Mode (Pixel ID=0, PHA=1) |
| ALE | 8086 address latch enable |
| WR* | 8086 write strobe |
| RD* | 8086 read strobe |
| 3.2 MHz | pixel section clock; this may be used for the 8086 bus timing |
| Pixel[0..7] | Pixel ID byte; high 4 bits are the FEA number and the low 4 bits are the pixel number |
| Etrig | Event trigger; Pixel[0..7] and Energy may be processed at the leading edge of this trigger. PHA is also started and DPU[0..7] is latched |
| Energy | The peak detector output of the active pixel is switched to this line |
| Calibrate | 1 kHz 0 to 5 V square pulse |
| Reset | Power on and software reset |
The DPU section controls the Address/Data bus. This bus should be driven except during read operations. When SEL* and RD* are both asserted, the pixel section will put data on the bus. To avoid bus contention, the DPU section should delay driving the bus for a minimum of about 100 nsec after RD* ends. SEL* should remain asserted for about 10 nsec after WR* or RD* end. Similarly, the address on AD[0..15] should persist for about 5 nsec after ALE ends.
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