Main Electrical SSD Components

Purpose:   Design the interface between the sensor (pixel) section and the DPU section. Include a pulse height analyzer and data accumulation electronics. Supply the DPU section with an event timing signal and a pixel ID byte. The DPU section should supply an 8086 style interface to read the spectra and program (set-up) the pixel section.

• A 240 pixel sensor
• 240 amplifiers
• 15 FEA gate arrays; each contains 16 amplifiers, 16 peak detectors, control logic, and coincidence circuity
• One PHA/scaler gate array which processes and routes all data to the RAM
• One 16K x 8 RAM. This is divided into two buffers. One may be read while the other is accumulating 8 spectra (based on time-of-flight) for each pixel. Each spectrum contains 16 energy channels; the storage per channel is two bytes.
• One ACTEL ACT1 FPGA; this controls the data accumulation and resets the FEAs after analysis
• One I/O support gate array; this generates the 3.2 MHz clock and provides the calibration pulser
• Buffers for every signal between the pixel and DPU sections
• Gating logic to isolate the 8086 bus from the FEA gate arrays except during set-up
• A 4-bit address latch controlled by SEL* and ALE to latch AD[6..9] for the FEA decoder
• 4 to 15 line decoder for FEA chip selection
• A 4-bit address latch controlled by SEL* and ALE to latch AD[12..15] for PHA decoder and RAM
• A 4-bit 2:1 MUX to route 4 additional address lines (the PHA only controls 13 address bits) from either the FPGA or the 4-bit latch to the RAM; SEL* and RD* control the MUX