Taylor University HENA CDR July 9 & 10 1997
IMAGE Front-end Gate Array Features
- 16 amps -- each has a calibration pulser input, low gain (proton mode) and high
gain (electron mode) sections, and test outputs via a diagnostic MUX for
- 17 peak holding circuits -- 16 XY pixels and on E detector pixel.
- 16 electron mode comparators with individually adjustable thresholds.
- 16 proton mode comparators with common adjustable reference.
- Micro computer data input to configure the chip.
- Logic disable gates for each pixel and each anti.
- Set-up latches (113 bits) to configure the chip.
- Mode control latches.
- Coincidence logic with adjustable resolving time.
- Programmable anti coincidence logic including pile-up rejection.
- Tri-state outputs controlled by a polling clock.
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